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Altera_Forum
Honored Contributor
Honored ContributorNIOSII addressing for 32 bit wide SDRAM
Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_ForumHonored Contributor
Honored ContributorIt is difficult to say what would be a good or bad constraint without knowing the design. I would take a look at the Timequest documentation to learn the best practices. Also for the SDRAM you have added it's automatically generated constraints to your Quartus project correct?
