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Altera_Forum
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15 years ago

NIOSII addressing for 32 bit wide SDRAM

Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The IOWR/IORD macros assume word addressing (32-bit). I recommend being explicit and just use the width specific macros: IORD_<8/16/32>DIRECT and IOWR_<8/16/32>DIRECT. This way you can use them to access narrow data and won't have some confusing mix of the two macro types in your code.

So by using the _32DIRECT macros you are correctly incrementing the address by 4 bytes at a time.

To debug the issue you are seeing I recommend simulating the design. Write a few values out to the memory and then read them back and watch the transactions on the fabric to see if you are getting what you expect returned in hardware.