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For a simple regular design like this, it seems the workaround would be to use SOPC builder to make a single unit consisting of one cpu with local memory and a FIFO with an exported avalon slave connection at the top level, and then bolt together multiple instantiated copies of the unit in Verilog.
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That worked well. To see how far the resources would stretch, I built a system of 83 Nios2/e processors with 512 bytes of local RAM each. SOPC builder needed only about 3 minutes to generate one unit. Synthesis took another 4.5 hours, but fitting that much logic into a chip is probably quite challenging.
Why 83 cpus? It seems the important limit is not memory bits but memory blocks. A Nios2/e (without JTAG debug) needs two M4Ks. Allowing another M4K per cpu for local RAM, 83 cpus will use 249 of the available 250 memory blocks.
Curiously, the final report says 424,960/1,152,000 (37%) of memory bits used, which suggests that the two M4Ks used internally by the Nios2/e are not very full. Is there a Nios2 architecture document anywhere which might explain this further?
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