Honored Contributor
Honored ContributorI've got my DE2-70 now and have tried some experiments.
The hardware does have plenty of capacity for multiprocessors: a ring of 16 Nios2/e cpus, each with 4KB on-chip RAM and a FIFO connecting to its neighbour, takes 17035 LEs and 540672 bits of memory -- 25% and 47% respectively of EP2C70 resources. Using the Nios2/s increases resource usage to 47% of LEs and 54% of memory (the extra RAM goes into instruction caches). The software, on the other hand, seems to have trouble coping with a design of this size: SOPC builder takes 2 hours 45 minutes to generate the system from a total of 81 modules. This is with Quartus 9.1 web edition on Linux -- is this version deliberately crippled to encourage sales of the subscription edition, or is SOPC builder just a toy for making systems of just a few components? For a simple regular design like this, it seems the workaround would be to use SOPC builder to make a single unit consisting of one cpu with local memory and a FIFO with an exported avalon slave connection at the top level, and then bolt together multiple instantiated copies of the unit in Verilog. Is that the usual procedure for large designs?
