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You have external memory interfaces on that board so I recommend dropping some pipeline bridges into the system if you attempt to hook up 16 processor cores to the memory otherwise the Fmax of your system will take a pretty hefty hit.
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I wouldn't expect to connect 16 processors to the same external memory. What I have in mind is a systolic array pattern where data flows between neighbouring processors, and only one or two cpus at the edge need to see the outside world.
But thanks for the pointer to the system frequency paper, which looks very useful.
Honored Contributor
