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Altera_Forum
Honored Contributor
16 years agoThe processor core uses two M4K blocks if I remember correctly for the register file. The debugger module uses one as well so you might need to go light on dedicated on-chip memories in your design. You have external memory interfaces on that board so I recommend dropping some pipeline bridges into the system if you attempt to hook up 16 processor cores to the memory otherwise the Fmax of your system will take a pretty hefty hit.
See "Increasing System Frequency" in this doc for more information about where to drop the bridges down in your design: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf