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Altera_Forum's avatar
Altera_Forum
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13 years ago

Nios2 instruction and data master ports could be variable width when cache is used?

Hi, I was thinking about the Nios2 architecture today and I have to ask why the Nios2 doesn't employ a variable width instruction and data master port when the Nios2 is configured to use cache?...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for that explanation.

Yes, FPGAs are growing in size, perhaps employing dedicated Nios2 masters for different purposes in such situations might result in more logic, but also simpler, and possibly also faster in-parallel, logic. We might need to move up from the nios2/f to the nios2/ turbo model :-)