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Altera_Forum's avatar
Altera_Forum
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13 years ago

Nios2 instruction and data master ports could be variable width when cache is used?

Hi, I was thinking about the Nios2 architecture today and I have to ask why the Nios2 doesn't employ a variable width instruction and data master port when the Nios2 is configured to use cache?...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Furthermore, even with a half-rate controller for a DDR 16 data pin interface, we can end up with a 64 bit avalon memory mapped slave.