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I suspect it would be a lot of logic for a small gain in very few configurations. FPGA pins ar usually at a premium - so a 64bit external data bus would be unusual.
There are a lot of other places where a relatively small amount of logic would improve performance in configurations that are more likely to be used.
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Since, presumably, this extra logic would be instantiated only in situations where it was useful, then then the issue occurs only for the person who maintains the Nios2 IP, and we wouldnt have concerns about excessive logic consumption in the FPGA.
My
naive perspective is that, when there
is a cache in the Nios2, the logic for copying from memory to cache wouldnt be complex, and maybe supporting different instruction and data port widths wouldnnt be a burden.
Jeff
Honored Contributor
