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Altera_Forum's avatar
Altera_Forum
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13 years ago

Nios2 instruction and data master ports could be variable width when cache is used?

Hi, I was thinking about the Nios2 architecture today and I have to ask why the Nios2 doesn't employ a variable width instruction and data master port when the Nios2 is configured to use cache?...
Altera_Forum's avatar
Altera_Forum
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13 years ago

I suspect it would be a lot of logic for a small gain in very few configurations. FPGA pins ar usually at a premium - so a 64bit external data bus would be unusual.

There are a lot of other places where a relatively small amount of logic would improve performance in configurations that are more likely to be used.