Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Also, have you compiled everything (including the BSP and libc bits) with -O2 or -O3, without those there will be a lot of cycles to the stack (which will almost certainly also be in your DDR memory). Even with a data cache the stack will probably be displaced from the cache by your sequential memory accesses. --- Quote End --- I have not tried to modify the compiler flags yet. Would it be better to connect the DDR as just another data master/slave to the CPU while using internal memory for the instructions?