NIOS with DDR as Main Memory

The compiler won't do anything special, all the writes from the NiosII cpu instruction unit are single words.

It would be normal to use the data cache for external memory (DDR or SDRAM), cache line writes are likely to be burst transfers.

I also believe the Avalon slave interface to DDR/SDRAM will merge writes to adjacent locations into a burst transfer to the memory itself. Certainly the first 2 writes are 'posted' (ie the data and address are latched and the Avalon bus cycle completes before the memory cycle starts).