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Kevin26's avatar
Kevin26
Icon for New Contributor rankNew Contributor
2 years ago

NIOS V/m SC.W instruction generating Illegal Instruction Exception

I have ported the RTEMS RTOS over to the NIOS V/m processor. During a context switch, there is a dummy sc.w instruction to clear any reservations. When this instruction is executed, an illegal inst...
Nios Cpu
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Kevin


If you are running LR/SC instruction, the instruction set is part of the Atomic extension set for RiscV.

Sorry to inform that it is removed from NiosV, and it is the cause of the illegal instruction message that you are seeing now.

For now there is no plan to add in the RiscV Atomic extension into for NiosV.


Regards

Jingyang, Teh