Nios V not working

After compiling the design, run the below command for generating the BSP and elf.

niosv-bsp -c --quartus-project=../pcie_ed.qpf --qsys=../sys.qsys --type=hal bsp/settings.bsp
niosv-app --bsp-dir=bsp --app-dir=app --srcs=app/main.c
echo "done1"
cd app
cmake -B build
cd build
make
echo "done2"
quartus_pgm -c 1 -m jtag -o"p;../../../pcie_ed.sof"
echo "done3"
niosv-download -g app.elf

echo "done4"
juart-terminal --instance 0 --device 1

Design 1: Nios V example design

Design 2: Nios V example design + 2 avmm pipeline bridge

I am using the original design and change the base address to the same as design 2 without adding the pipeline IP , the hello world is not working as well.

Design 3: Design 1 + change base address to the same as Design 2

Now I use Design 2 and manually change the base address for cpu, ram, jtag uart to the same as Design 1 and random base address for the 2 avmm pipeline bridge. It is working now. I would like to understand

1) Why the base address automatically assigned by Quartus Platform Designer did not work?

2) Does the niosv-bsp and niosv-app have dependency on the base address?

3) If #2 is true, can you teach me how to use these 2 commands? the command --help did not explain much about the RAM base address

Thanks for helping.

Hi,

Noted on your question in this case. Please give me some time to look in to this. May I know the devkit and Quartus version that you using in this project?

Regards,

Kelly

Hi,

You can check out this link: https://cdrdv2-public.intel.com/750761/ug-726952-750761.pdf and have a look at the section 2.1.3 Specifying Base Addresses and Interrupt Request Priorities.

Thank you.

Regards,

Kelly

Hi,

Any updates from your side?

Regards,

Kelly

Quartus 22.3 and Agilex devkit

It seems like any base address can bet set for on chip ram, not necessary from 0x0. Correct me if I understand wrongly.
In the design it is not working, can you try the Qsys files provided earlier and share if you can run the non 0x0 on chip ram base address ?

Hi,

Apologies for the delay but I will need some more time to test out the .qsys design that you sent and will update you. Do let me know if you have any further findings. Thank you.

Regards,

Kelly

Sure. Thanks

Hi,

Is there a reason why you would want to change the base address to non 0x0? It is not advised to do so.

The application execution starts from on-chip RAM base address 0x0, if we change its base address then reset vectors need to be updated as that is where Nios will look to starting the execution of application. This might be the root cause why the design is not working.

Thank you.

Regards,

Kelly