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Chris039's avatar
Chris039
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Nios V not working

Hi, I am using example design created in https://www.intel.com/content/www/us/en/docs/programmable/726952/22-1std-1-0-0/processor-example-design.html I changed the loop from 1000 to 10 in ma...
  • KellyJialin_Goh's avatar
    KellyJialin_Goh
    3 years ago

    Hi,

    Yes, the application execution starts from on-chip RAM base address 0x0.


    Thank you.

    Regards,

    Kelly


Chris039's avatar
Chris039
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Now I use Design 2 and manually change the base address for cpu, ram, jtag uart to the same as Design 1 and random base address for the 2 avmm pipeline bridge. It is working now. I would like to understand

1) Why the base address automatically assigned by Quartus Platform Designer did not work?

2) Does the niosv-bsp and niosv-app have dependency on the base address?

3) If #2 is true, can you teach me how to use these 2 commands? the command --help did not explain much about the RAM base address

Thanks for helping.