Forum Discussion
Greetings,
This seems to be a reset issue. The Reset Release IP is missing from your platform. You may refer to the Nios V application note: https://www.intel.com/content/www/us/en/docs/programmable/784468/current/an-985-processor-tutorial.html
You can follow the steps in 1.2.1 section (1.2.1.1.2.4. Adding Reset Release Intel® FPGA IP).
Furthermore, you may refer to the design examples available for Agilex 5 development kit:
1- Agilex™ 5 - Hello World on Nios® V/g Processor Design Example
Thank you,
Fawaz.
- JMX4 months ago
New Contributor
Hi, I have tried to change my design but still shows this output when I run the command NIosV download. I will have a look at the links you attached, thank you so much for your quick reply!
- JMX4 months ago
New Contributor
And also I have tried the ready-to-test in this link https://github.com/altera-fpga/agilex5e-nios-ed. I download the .sof file to the board through Quartus Prime Pro 25.1 -> Tool -> Programmer -> Change File ->top.sof, then run the command NiosV download, the command shell still shows the error.