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andy25's avatar
andy25
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Nios V exception code

I have a Nios V and an "Avalon FIFO Memory Intel FPGA IP" fifo I'm trying to read in C.

I can read the status and length just fine:

// works
int len = altera_avalon_fifo_read_level(IPMB_FIFO_IN_CSR_BASE);
// works
if(!altera_avalon_fifo_read_status(IPMB_FIFO_IN_CSR_BASE, ALTERA_AVALON_FIFO_STATUS_E_MSK))
{
   // dies
   int sample = IORD_ALTERA_AVALON_FIFO_DATA(IPMB_FIFO_OUT_BASE);

in gdb, I can see IORD causes an exception_code 4:

Program received signal SIGTRAP, Trace/breakpoint trap.
handle_trap (cause=4, epc=1512, tval=134414729) at HAL/src/alt_irq_handler.c:106
106	            NIOSV_EBREAK();
(gdb) p exception_code 
$4 = 4
(gdb) p is_irq
$5 = 0

Whats an exception code 4? Is there a list someplace?

Is *_FIFO_OUT_BASE the right thing to pass to IORD_ALTERA_AVALON_FIFO_DATA?

Thanks for your time,

-Andy

6 Replies

  • andy25's avatar
    andy25
    Icon for Occasional Contributor rankOccasional Contributor

    The problem was caused by Platform Designer's System -> Assign Base Address to assign the FIFO's out base address to an odd number.

    When I change the base address (IPMB_FIFO_OUT_BASE) to an even number it no longer crashes.

    I'm still curious where I can find a list of exception codes, or find info about what a 4 means.

    -Andy

  • Hi,


    Thanks for the feedback on the Platform Designer, I will channel this to our internal team.


    Regarding the exceptions code 4, I will check on my side and get back to you.


  • Hi,


    I am still trying to get the info on the exception code, I shall get back to you.


    • andy25's avatar
      andy25
      Icon for Occasional Contributor rankOccasional Contributor

      Nope. Everything runs fine as long as I have an even base address.

      After running the Auto Assign Base Address thing, I just have to remember to check them.

      -Andy

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