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linhviet306's avatar
linhviet306
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1 year ago

Nios V Ethernet failed on Cyclone V GT development kit

Hi, I'm currently learning to transfer data through Ethernet using Nios. Since I use Quartus Prime 22.1, the niche stack isn't there anymore, so I tried to use Nios V and uC/TCP IP base on the CVGT simple socket server reference design, I changed the SGDMA to mSGDMA, Nios II to Nios V. Everything else is exactly as in the reference design. The project compiled fine (although there is some timing requirement error on the nios_cpu sdram). I tested the Nios V with the code from the Arria 10 uC-TCP simple socket server. The processor started and failed at Auto-negotiation.

Can you guys help me please?

14 Replies

  • linhviet306's avatar
    linhviet306
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    Updated on my progress. So I increase the autonegotiation timeout from 2500 to 5000, and got this error

    • linhviet306's avatar
      linhviet306
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      Next update, so I increase the mSGDMA to 2K, and the PHY is instantiate succesfully. But, after that, it got stuck at Simple Socket Server listening on port 80, can't ping or using Telnet to connect. Any idea how should I debug this?

  • tehjingy_Altera's avatar
    tehjingy_Altera
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    Hi


    I am Jingyang and will be helping out on this case.

    When you mention you increased the mSGDMA to 2K are you referring to the buffer size?


    When it is on listening, that means you are able to connect to it by ssh.

    Try using another device (using Putty or Telnet) and connect to 192.168.1.234 with port 80.

    You should be able to receive some logs from the board.


    Regards

    Jingyang, Teh


    • linhviet306's avatar
      linhviet306
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      Hi Jingyang, thank you for your support!

      I did try with putty and it said connection time out. I started debug and tried to ping from the board and it failed. The NetBuf_Get method failed. I noticed the Tx led is always on. So I think there maybe some error with the buffer address pointer of the mSGDMAs or TSE.
  • tehjingy_Altera's avatar
    tehjingy_Altera
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    Hi


    Just asking the ethernet cable setup, did you connect the ethernet cable to your laptop or it is through a router?

    For static IP you would need to connect the board ethernet directly to your laptop ehternet port. After that in the laptop ethernet setting set the ip address to ip mentioned in the board.

    https://www.trendnet.com/press/resource-library/how-to-set-static-ip-address


    Besides that you could remain your current setup and change the IP from static to DHCP.


    Regards

    Jingyang, Teh


    • linhviet306's avatar
      linhviet306
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      Hi,

      I connect the board directly to my laptop and use static IP. Can't ping the board or ping from the board. I tried to use packet sender to send UDP data to the board to see if the core can receive anything but it didn't trigger the receive routine in mSGDMA. How should I process?

      By the way reduce the SSS_TX_BUF_SIZE help me with the NetBuf_Get problem. Apparently the MTU size is less than the SST_TX_BUF + header, so it failed. Reduce the buffer size help the Tx trigger, but it still have timeout problem that Ping still failed.

  • tehjingy_Altera's avatar
    tehjingy_Altera
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    Hi


    That is weird.

    Looking back at your initial comment.

    You migrated the NiosII design over to NiosV and made some changes to the SGDMA.

    One suggestion is for you to try ou thte NiosV example design first and see how it goes.

    The design is based of the Arria10 but it would be able to be migrated to CycloneV.


    Regards

    Jingyang, Teh


  • linhviet306's avatar
    linhviet306
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    Hi,

    I did try with the Nios V design. The design for Arria 10 uses SGMII mode, I changed it to RGMII, but the problem still persist. I think there's some problem with the mSGDMA core using prefetcher core.

    Do you guys have any reference design for the msgdma using only standard descriptor without the prefetcher core. I was able to construct standard descriptor without prefetcher core and sent raw UDP frame. But I couldn't make the receive part to work.

  • tehjingy_Altera's avatar
    tehjingy_Altera
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    Hi


    Let me try to change example design to work with RGMII on the dev kit here.

    It might be a big change or not, let me try but no guarantee

    Please give me sometime to work on this.


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
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    Hi


    Happy New Year!

    I tried the example design and able to get it work without making any changes to it.

    But could not get it to change it to RGMII.

    Is there a reason why you would like to change the mode to RGMII?


    Regards

    Jingyang, Teh


    • linhviet306's avatar
      linhviet306
      Icon for New Contributor rankNew Contributor

      Hi,

      Thanks, and Happy New Year to you, too!

      My understanding is that Cyclone V GT kit doesn't support SGMII so I have to changed to RGMII mode. Is it not correct?

  • tehjingy_Altera's avatar
    tehjingy_Altera
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    Hi


    From the schematic i see that the CycloneV GT has RGMII as default.

    In your design the only changes you made are in the TSE IP where you change the Core Variant to "10/100/1000Mb Ethernet MAC" right?


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor

    Hi


    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



    Regards

    Jingyang, Teh