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Altera_Forum's avatar
Altera_Forum
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10 years ago

Nios stops after upgrading Hardware from SRAM to DDR3 RAM

Hi

I have upgraded a working design, which had a SRAM (For instruction and Data) and a SDRAM for big Data like Packets from the MAC.

The Hardware works so far, but my Software doesn't really...

Setup:

I added a datacache to the NIOS with 4kByte and increased the instruction cache to 32kBytes. I also added

the line "alt_dcache_flush_all();" bevor all DMA transfers which loads some data to the MAC.

I had the system once working for an hour, but normally it stopps transfering Packets after few seconds

without any error message.

My question ist:

How do I have to setup the system? Are there any helps how to setup caches and should I use bursts or not?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Could you share your design? If your mixing SRAM and DDR3 , you need to make sure the instruction and reset vectors are pointing to the correct location. Sometimes if not it can cause strange stuff to happen. Also if DDR3 isnt set up correctly, such as not having the correct timing and such for the board can cause issues. Try to see if you can write and read to the DDR3 with the old setup. If the DDR3 works fine, then try upgrading again. Hope this helps.

    -Trukng
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi Trukng

    Sorry, I can't share my design.

    I don't mix SRAM und DDR3. I have replaced an old SRAM und a SDRAM. Now I only have one DDR3 RAM for my NIOS. I'm trying to setup everything correctly, but there are just too many options like:

    icache

    dcache

    burst/no burst

    and in the DDR3:

    burst size

    reordering

    errorcorrecting

    I realized, that my dcache should be at least 32kByte. Then I don't have some system crashes. But the TCP-IP is not as fast as it was with the old SRAM/SDRAM.

    I think it has to do with the line "alt_dcache_flush_all();". I think this process of flushing the dcache needs a lot of time.

    I did some testing with the EMIF and everything seemd to be green, so my hardware design is ok.