I usually put the SOPC component as an instance of the top level to enrich my design with other components (like in your application: pll, reset and some signal conditioning).
Being the design one level down in hierarchy, I usually double check that the constraints still match the names of the pins. Once I missed to check the DDR2 pins and the design did not work properly, for example. I think that triple speed ethernet is as delicate as the memory controller so you may have some failed paths that are not recognized by the timing analyzer.
Let me know.
Regards,
Gabriele