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Altera_Forum's avatar
Altera_Forum
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19 years ago

NIOS Register Bank Access

Hi

I am using Nios/f CPU at 100 Mhz and developing USB2.0 HAL driver.

When device send an interrupt to the NIOS CPU ,it does two thing:

1. Push all the current content on stack memory

2.Execute ISR.

Here when device send interrupt,nios take 1.5 micro second to start ISR.I want to reduce this time by using some custome instruction or by any mechanism.

I am using Tightly couple memory and also on-chip memory for reducing Interrupt latency. Here i am using on-chip emory for stack.

One suggestion in my mind is that if i can shift or transfer whole nios register bank directly to stack (which actualy NIOS HAL is doing when interrupt come from device)then might be i will get more time to serve my ISR. I have total 3.7 micro second for this and out of them 1.5micro second will take by NIOS.

If anybody have an idea or any custome instruction for nios register bank access then plz let me know.

Best Regards,

slsnios

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Hi,

    1.5µs is not too bad. Fiddling with the interrupt handler itself can reduce a little bit. I have 1.8µs on 50Mc, so maybe you can go down to 0.9µs. Depends also a lot on the performance of the memory you store the processor register in.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Hey 1.5 usec is too much for me..i just want to complete it within 1 usec.Is there any way.If then plz let me know..very fast....