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I suspect the RAM or the interface to the RAM first. Try holding the NIOS in reset much longer than the DDR controller and see what that does.
Jake
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An update.....
I did what you suggested. I isolated the reset to the processor & made the reset pulse to the processor longer (increased from 870 ns to 1.4us). Initially, this did not make a difference.
I then changed the logic that resets the processor so that I could reset just the processor from an external switch. The processor would successfully reset & execute code when the switch was pressed.
I then modified the processor reset logic to remove the external reset, and to make the pulse width REALLY long (5 seconds). This did the trick. The system would now take a reset from the watchdog timer & the processor would start up & execute code. Before, when a configuration & reset was initiated from the watchdog, the FPGA would configure, the non-processor FPGA logic would run, but the NIOS would not start.
After some experimentation, I discovered that I could make the processor pulse width as short as 360ms & the processor would successfully reset & execute code. Any shorter, & I would see the original problem.
Right now, I believe that there is some sort of race condition with the processor & the way the memory subsystem is starting up. I modified the FPGA design so that the processor pulse width is 670ms & is a separate signal from the reset signal that resets Flash & DDR DRAM controller. The Flash & DRAM controller reset signal is asserted at the same time, but only is 870ns wide.
I successfully tested the change on both boards that previously exhibited this problem. I also successfully tested the change on boards that previously were working. Finally, I did some repeat testing on one of the boards that previously failed by forcing a watchdog timer reset >10 times. Each time, the system would now come up & run properly.
Due to time constraints, this is as far as we're going to take this problem at this point unless it resurfaces.
Thanks for all your help & your suggestion.
Fred O
Honored Contributor
