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Altera_Forum
Honored Contributor
16 years agoNIOS Processor Fails to Reset
We're using a Cyclone III FPGA with a NIOS processor & custom designed logic. The system was built using Quartus V8.1. A configuration sequence can be forced via an external watchdog timer. When the ...
Altera_Forum
Honored Contributor
16 years agoWhat is the reset address of the processor and where is it located (flash, serial flash, onchip RAM, etc.)? Is execution code being copied to the DDR DRAM before execution? Are you sure it's not a DRAM problem?
I suspect the RAM or the interface to the RAM first. Try holding the NIOS in reset much longer than the DDR controller and see what that does. Jake