NIOS memory usage

Using the 9.0 IDE I had to generate my own linker script (which it really doesn't want you to do) in order to get the code and data assigned to correct memory areas.

However since I'm loading code through a external interface (custom vhdl generating avalon writes - will be a PCIe slave) I don't need the jtag debug (it actually gets in the way) and am now building using versions of gcc and binutils compiled from the tarball downloaded from Altera's web site - without using any of their IDEs (etc).

My Nios code/data blocks get converted into ppc object file data blocks and then linked into a ppc program which is also linked with the nios symbol table! This saves worrying (too much) about binary compatibility between the fpga code and the program that drives it - everying is compiled and linked on the same system by one makefile.

I am going to have to sort out the 9.1 IDE to do some tests of custom instructions on a standard (cyclone III) eval board - without having to get our hardware guys to rebuld the main fpga image for me.