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Altera_Forum
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16 years ago

Nios interrupt response time

I have a custom SOPC component which has an interrupt sender (irq_n) in it's avalon interface. In my SOPC component HDL I set the irq_n line low, which causes a Nios interrupt handler to fire. In the...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's a standard Nios (-s). There is an instruction cache but no data cache. The memory is SDRAM (part no = MT48LC16M16A2P-75) clocked at 80MHz. The sdram settings in SOPC builder are:

CAS latency cycles = 3

Initialization refresh cycles = 2

Issue one refresh command every = 15.625us

Delay after powerup, before initialization = 100us

t_rfc = 66ns

t_rp = 20ns

t_rcd = 20ns

t_ac = 6ns

t_wr = 20ns