Nios instruction timings

I've located the undocumented stall.

There is a 1 clock delay if a read follows a write to the same tightly coupled data block.

The same delay may apply to data cache accesses.

The reason is that the write cannot be requested unless the address matches and the instruction is a write.

The read can (and is) issued to every tightly coupled memory block every cycle, and the value only used if the instruction was a read on that block.

This means that the writes actually happen one clock later than reads.