NIOS II/F With No JTAG

Hi all,

I have a NIOS II/F design which has level 2 debug with JTAG UART.

We want to remove it for various reasons now our production devices can load its own code from ROM.

However, if I cange the debug level to 'no debug' in SOPC builder I get the error

"cpu: Unknown Break Location CPU/JTAG_DEBUG_MODULE"

The problem is I can't change that location in the 'more CPU settings' tab, so I cant clear the error and generate the design!

Any ideas on how to remove the JTAG uart?

[I'm using Quartus 6 and SOPC builder 6 Build 178]

TIA

Tom