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Altera_Forum
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14 years ago

Nios II/f performance on Cyclone IV E

Hi, I am trying to evaluate Nios II/f on a dev. board fitted with EP4CE55F23C7. I've ported the Cyclone III Dhrystone example from Altera (Fast Nios II Hardware Design Example) to my board....
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thanks for the info. The problem seems to be in the compiler - dhrystone test compiled

with gcc 4.1.2 estimates 0.62 DMIPS/MHz and with gcc 3.4.6 1.04 DMIPS/MHz. It

doesn't matter which version was used to compile the BSP, just the dhrystone itself.

I've used the same makefile / compiler flags, but changing e.g. optimization level doesn't

yield much difference with 4.1.2. I didn't investigate this any further, but obviously it's

something to keep in mind.