Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Nios II/f performance on Cyclone IV E

Hi, I am trying to evaluate Nios II/f on a dev. board fitted with EP4CE55F23C7. I've ported the Cyclone III Dhrystone example from Altera (Fast Nios II Hardware Design Example) to my board....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You might have a clock crossing adapter in the memory path. Make sure the Nios II core and the memory are on the same clock domain otherwise each memory read will take around 9 clock cycles which will have a huge impact on the Dhyrstone algorithm. Also make sure the timer resolution is the same as the orginal design, if it's set to fine then the CPU will get blasted with interrupts and take longer to complete the benchmark.