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Honored Contributor
Honored ContributorNIOS II/f core
I create system design based on NIOS II/s core (insrt cahe 512 bytes). In my design programm and data memory located in SRAM (Cyc. dev board). RESET and ISR code in on_chip RAM. My program work ...
Altera_ForumHonored Contributor
Honored ContributorThe are two potential reasons why your Nios II/f fails.
There is a known bug in the Nios II/f data cache in release 1.0 that shows up on Cyclone. A fix for this bug will be released in a few weeks with the Nios II 1.0.1 release. The bug is a rare case that only shows up in unoptimized code. So, as a quick experiment, make sure all your code is compiled with optimization enabled. The other possibility is that the data cache isn't being bypassed/flushed consistently by the software. The Nios II/f uses a writeback cache so if software bypasses the data cache on a store and then uses a normal load that reads the value from the data cache, the most-recent value of that address won't be returned. This is not a bug in the data cache but is a bug in the software. Can you tell me more about your SOPC Builder system and the software you are running?
