Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Nios II/e clone

Hello, I wrote a Nios II/e CPU clone in verilog. It takes between 600 and 800 LEs and executes most of the instructions in 4 cycles. It comes with an ISS and a trace tool. Verilog simulation a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hello,

I have added a big endian option in the core.

Is there an easy way to tell GCC to generate big-endian code ?

Regards,

Frederic