NIOS II Stratix board pin map

Thanks Kerri, for a prompt reply.

I am working with NIOS II, with quartus II 4.2 SP1 and NIOSII IDE 1.1. There is no csf file existing in the "standard" project directory. I double-checked the pin-map I have created using my own tcl script with that of the standard design. Just for the heck of it, I have kept all the modules and their base addresses identical to that of the standard design. However, I am not using the bdf file for top level entity generation, and including SoPC builder-generated vhdl file in the quartus project.

Am I missing a crucial pin-out? I have simulated the design and a simple program in Modelsim and it works fine. When I try to debug, the debugger doesnot show me the source statement @ which the processor is presently halted, but goes in a loop and loses control after a while.

Thanks and regards,

Ajit