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Honored Contributor

19 years ago

NIOS II SPI

I have some problems using NIOS II SPI pheriperal on a CYCLONE FPGA. It seems that the SCLK signal is driven only for the size of word I've configured in the SOPC builder, while it should be...

Altera_Forum

Honored Contributor

19 years ago

- that's the normal way spi works

- there is one clock cycle on SCLK for every data bit shifted out

- SCLK is independent of SS_n

see e.g.

http://www.maxim-ic.com/appnotes.cfm?appnote_number=802 (http://www.maxim-ic.com/appnotes.cfm?appnote_number=802)

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NIOS II SPI

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