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Honored ContributorNIOS II SPI
I have some problems using NIOS II SPI pheriperal on a CYCLONE FPGA.
It seems that the SCLK signal is driven only for the size of word I've configured in the SOPC builder, while it should be driven for the time the chip select (SS_n) signal is asserted. Did anyone experience my same problem ? How can I workaround it ? Best Regards /Alessandro Strazzero1 Reply
Altera_Forum- that's the normal way spi works
- there is one clock cycle on SCLK for every data bit shifted out - SCLK is independent of SS_n see e.g. http://www.maxim-ic.com/appnotes.cfm?appnote_number=802 (http://www.maxim-ic.com/appnotes.cfm?appnote_number=802)
