Altera_Forum
Honored Contributor
19 years agoNIOS II SPI
I have some problems using NIOS II SPI pheriperal on a CYCLONE FPGA.
It seems that the SCLK signal is driven only for the size of word I've configured in the SOPC builder, while it should be driven for the time the chip select (SS_n) signal is asserted. Did anyone experience my same problem ? How can I workaround it ? Best Regards /Alessandro Strazzero