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BeB
Occasional Contributor
Occasional ContributorNIOS II SPI number of slaves
Hello,
I am using Quartus 19.1 and have a Qsys NIOS II processor with a 3 wire SPI core. I setup the number of slaves to be 20, which is consistent with the generated VHDL code, as the slave selec...
EricMunYew_C_Intel
Frequent Contributor
Frequent ContributorCan you try to generate Verilog.
BeBHello,
I didn't try Verilog and made everything work with 16 bits instead.
BeB.
