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Altera_Forum's avatar
Altera_Forum
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9 years ago

NIOS II SPI multiple slave environment

Hi all,

I am trying to communicate to multiple SPI slaves (ADC and a DAC) using Altera DE2 board as SPI Master for 8 bit transfer and 2 slaves SS_n[0] and SS_n[1] in SOPC builder. In the NIOS II code, I assert the respective SS_n to low only when I intend to perform read/write operation on the respective slaves. This is very well visible from the attached pictures. In first one, SS_n[0] is low till the time I write 2 bytes, while in the second one, SS_n[1] is low till I write and read back 3 bytes. Both operations seem mutually exclusive to me, but I can not observe the correct data being read into ADC or written from DAC either.

What could be the possible problem here, as I am able to successfully read from ADC when configured in single slave mode?

Few more details:

Altera DE2

Quartus v9.1

NIOS II SBT v9.1

ADC: MCP3208

DAC: MCP4922

SCLK: 500 kHz

GPIO[0-4]: MISO, MOSI,SCLK, SS_n[0], SS_n[1]

http://www.alteraforum.com/forum/attachment.php?attachmentid=12527&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12526&stc=1

Please let me know if more details are required.

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    There could be a number of reasons causing your problem.

    As you said, SCLK and SS signals seem to be correct, but you should capture MISO and MOSI as well: check if they comply with ADC and DAC specification. Also check if you are using correct settings for clock polarity and phase.