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Honored Contributor
15 years agoTo give you all metrics, I had a design with a streaming port on a sgdma, feeding 16 M2K fifos through a channel demux -
when I found that channels were not supported I changed to a mem mapped setup using a pipeline bridge feeding 16 M2K fifos in a 3c120, the latter implementation synthesized 7% larger pretty much across the board in LE, comb and dedicated logic