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Altera_Forum
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16 years ago

Nios II reset_n pulse requirements

I am creating logic in my FPGA that can reset the Nios II processor. How long does the low pulse on reset_n have to be and is there anything else I should know? I will have a Nios II processor, sev...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Thanks for the quick reply! That's just what I needed.