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Altera_Forum's avatar
Altera_Forum
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16 years ago

Nios II reset_n pulse requirements

I am creating logic in my FPGA that can reset the Nios II processor. How long does the low pulse on reset_n have to be and is there anything else I should know? I will have a Nios II processor, several Avalon MM peripherals, and custom logic functions.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It must be at least two clock cycles of your slowest clock in your SOPC Builder system (I would go with more than 2 for good measure). It'll get synchronized to all the clock domains used in your SOPC Builder system. The reset behavior is as follows:

    1) The system will be asynchronously reset

    2) The system will exit reset synchronously