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Hi folks,
Is it safe to assume that the outputs from an embedded NIOS II can be used in other areas of the FPGA logic without worrying about metastability. In the case in question, The NIOS and logic are both being driven from the same PLL, but using different taps. The logic is at 400MHz and the NIOS at 100MHz.
Will I be free of metastability issues? My immediate assumption would be yes but that is an assumption.
Many thanks
deBoogle
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You need follow same rules of clock domain transfers. In this case if fpga clock is 4*nios clock and are in phase then the two clocks will always be related in same way so you don't need resync of logic and timequest will report if any violation occurs across.
Honored Contributor
