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Altera_Forum's avatar
Altera_Forum
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21 years ago

Nios II on HC device

Hi all,

It seems that Nios II use *.mif file to initialize cache tag memory. We can find "dc_tag_ram.mif" and "ic_tag_mem.mif" file in project directry.

Cache tag is RAM, so I think this means Nios II need pre-loaded RAM feature.

Other side, HardCopy device does not support pre-loaded RAM feature, I heard.

If cache tag contents are un-defined at reset time, I think Nios II does not run correctly. But Altera says Nios II support HC Device. What is wrong in my thinking?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    There is an open problem report on this. It's being worked on.

    If you have a Nios II design that you need to go to HC with now, please email me off line.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    Thank you, Kerri.

    This question is just only my interest. I wait the future release.

    Could you describe how to avoid this problem in the future release? (If that's not a confidential information.)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    The MIF files for the cache contain random values to make the FPGA RAMs behave like uninitialized

    hardcopy RAMs. I did this so that we could be confident that the caches would work properly on hardcopy.

    BTW, the register file RAMs also have MIF files that initilalize all registers to the value 0xdeadbeef

    including register 0. The reset logic sets register 0 to zero as is required for correct operation.

    Once again, this works properly on FPGA or hardcopy devices.

    The optional debug core features do rely on initialized RAMs for the Nios II 1.0 release.

    A future release of Nios II could allow the debug core to work on hardcopy but this

    wasn't considered critical for the 1.0 release.

    Maybe this is what Kerri was alluding to in her response. We don't expect many customers

    to put the debug core on their hardcopy devices because they don't want the overhead of it and

    should have already debugged their system using an FPGA.

    So, the Nios II CPU will work for our hardcopy customers. This is a strong

    requirement because we believe Nios II on hardcopy will be a popular option.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    James, Thank you for description.

    I did not know that cache tag value are random.

    But.. for example. If the debuging core could not be on HC device, I think there is no way to write external Flash via JTAG. My understanding is Flash Programmer needs this core.

    Anyway, I see that the future virsion of Nios II will support HC. That's good news.

    Thanks all.