Nios II on HC device

The MIF files for the cache contain random values to make the FPGA RAMs behave like uninitialized

hardcopy RAMs. I did this so that we could be confident that the caches would work properly on hardcopy.

BTW, the register file RAMs also have MIF files that initilalize all registers to the value 0xdeadbeef

including register 0. The reset logic sets register 0 to zero as is required for correct operation.

Once again, this works properly on FPGA or hardcopy devices.

The optional debug core features do rely on initialized RAMs for the Nios II 1.0 release.

A future release of Nios II could allow the debug core to work on hardcopy but this

wasn't considered critical for the 1.0 release.

Maybe this is what Kerri was alluding to in her response. We don't expect many customers

to put the debug core on their hardcopy devices because they don't want the overhead of it and

should have already debugged their system using an FPGA.

So, the Nios II CPU will work for our hardcopy customers. This is a strong

requirement because we believe Nios II on hardcopy will be a popular option.