nios II implementation problem

hi nipu_n,

in case your question is more basic:

Altera FPGAs are SRAM-based devices, other vendors provide FLASH-based FPGAs. So SRAM-FPGAs looses its content everytime power is removed. Everytime power is connected, the FPGA needs to be configured, that means loaded with your specific design. Because on-chip ROM is part of your design, it is initialized while configuring the device.

In a stand-alone application you have to add an extra FLASH-device (e.g. serial FLASH EPCSxx) which is programmed with your design and automatically loads your FPGA after power up (in milliseconds).

Mike