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Altera_Forum
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20 years ago

nios II implementation problem

Respected members,

I have some doubts on Nios II processors. I am requesting the forum members to clarify my doubt.

When designing NiosII processor system using SOPC builder, there is a on-chip ROM component inside the system. But the problem is that, the design is volatile, ie, when disconnecting the power, and again switching it on, again we need to program the FPGA. So my question is, what's the use of on-chip ROM. because whenever we there is a power off, data will vanish!!!.

please suggest a solution for this.

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