Altera_Forum
Honored Contributor
Honored ContributorNios II IDE v9.0 unexpected behavior
I am facing a strange behavior when using Nios II IDE!
I tried to re-use previous projects of mine (which had been built successfully), but this time a still problem occurs. when building such projects I get these error massages: --- Quote Start --- **** Build of configuration Debug for project memtest_0 **** make -s all includes Compiling altera_avalon_sgdma.c... /cygdrive/c/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sgdma/HAL/src/altera_avalon_sgdma.c: In function `alt_avalon_sgdma_do_sync_transfer': /cygdrive/c/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sgdma/HAL/src/altera_avalon_sgdma.c:206: error: `DC_FIFO_0_IN_CSR_BASE' undeclared (first use in this function) /cygdrive/c/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sgdma/HAL/src/altera_avalon_sgdma.c:206: error: (Each undeclared identifier is reported only once /cygdrive/c/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sgdma/HAL/src/altera_avalon_sgdma.c:206: error: for each function it appears in.) /cygdrive/c/altera/90/ip/altera/sopc_builder_ip/altera_avalon_sgdma/HAL/src/altera_avalon_sgdma.c:207: error: `DC_FIFO_0_OUT_CSR_BASE' undeclared (first use in this function) --- Quote End --- The problem occurs only with projects which have a Dual FIFO (not necessarily called DC_FIFO_0.) This error is the same for any project i try to build! I repeat that i previously built these projects and they worked properly. please if any one can explain what's going on cause it's urgent :confused:
