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Honored Contributor
Honored ContributorNIOS II EPCS bootloader
I have a Cyclone III and am trying to use EPCS to boot my NIOS II code. I can flash the device with the NIOS Flash Programmer without error but removing the JTAG header and cycling power doesn't appear to start my code. The Verilog code appears to be running. I've configured the NIOS reset vector to point to the EPCS flash controllers address. I've configured the syslib linker section as follows:
Program memory: sdram Read-only data memory: onchip_memory Read/Write data memory onchip_memory Heap memory: onchip_memory Stack memory: onchip_memory The syslib RTOS settings is set to "none (single-threaded)" Any debugging tips would be greatly appreciated! Thanks, Jim3 Replies
Altera_ForumLook at the final post of this topic (http://alteraforum.com/forum/showthread.php?t=5547) on Altera Forum and try the workaround that it mentions.
Cheers, - slacker- Altera_Forum
Thanks Slacker!
I'm trying it now. Its always nice to find these "undocumented features" in software you paid money for! Jim - Altera_Forum
Is this fixed in Quartus 9 SP2 ?
