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Honored Contributor
Honored ContributorNIOS II DMIPS
I tested MIPS in Nios II full feature with Dhrystone 2.1. as a result, cyclone ep1c20f400c7 Dev board's MIPS is about 35 DMIPS at 50MHz system clock. bus, stratix ep1s10f780c7 Dev board'...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- originally posted by kenland@Oct 18 2004, 09:25 AM while checking altera's website for the niosii update i noticed the footnote in the core summary table that shifts on cyclone are one clock cycle *per bit*. so our code that strips out individual bytes from long words using shift and mask is running 24x slower than on coldfire. (ouch) --- Quote End --- The optimizer doesn't recognize multiple-of-8-bit shift-and-mask operations as byte accesses? Oi! If all else fails, sounds like a plausible application for a custom instruction. You lose portability, though. Another thing you can do is, for example, typecast a long* to a char* if you have an array, or use a union if you have a scalar. Although those bring out byte-order issues.
