NIOS II Custom Instruction access to CPU Regs'

For what Avalon does for you don't expect one clock cycle. Just remember that most of the cores if not all are on that avalon bus. Like what was meantioned before, when you service an interrupt the state of the cpu must be saved which is a lot of data (control registers, and data registers).

ots_dev, the internal memory is used for the cache, but it is not accessed from the avalon bus, using the NIOS II pipeline they are able to effectively get the data out in one clock cycle. When accessing memory that you have added to your system (internal, sram, sdram, etc...) your transfers occur across the avalon bus (which may not be free so waiting may occur). The reason why I suggested internal memory, is that you do not want to be transferring to a slow storage device in your ISR (you can have as low of a latency as you want, but if your ISR is slow there is no point really).

I think for now the best you can do is implement this in assembly to cut the latency down. I haven't done any assembly on NIOS II yet, but on some other processors I have done things like skip saving the register set (set aside registers that I never touch to use in the ISR). But in most cases if I want a latency lower then what you are seeing I just do the algorithm in hardware and leave the processor out of the loop.

Good-luck