NIOS II Custom Instruction access to CPU Regs'

Holger,

Look at the processor documentation, paga 190 of the reference handbook (pdf page nr).

load and store with avalon transfer : >1 , so can be 100 without violating the spec. (So even with a single cycle RAM access, and no other peripherals accessing the bus at that moment (DMA transfers, instruction load, ...), it is more than one according to the spec. I don't think Altera will put '>' in the documentation if there is a chance to have a '>='.

load and store without avalon transfer = 1 --> so if cache is containing the data, it should be 1 cycle, this has nothing to do with ineternal or external ram. If an interrupt occurs, the caches will normally not contain the addresses of where you want to store the registers, and if thay contain them (e.g. when you just left a function with a big stack frame, and the addresses on the stack are reused for the interrupt stack frame), you can not count on it for maximum values.

Stefaan