Nios-II core reset

> However, I do like the idea of having a seperate reset for the NIOS II core ...

Agreed ... and I don't think this is unreasonable. For example, many

DSP architectures have this feature (being able to hold the core in

reset while an external master or 'host' initializes memory).

I tried creating two system modules: one with the n2 core (and a few

periperals), the other with my sdram and flash. The n2 core module and

a PCI interface have master interfaces to the memory module. All modules

were tied to hardware reset, however a reset signal from the

PCI module (not the PCI reset) could also reset the core module ... but I'm

having some troubles with this. (And I did gate the read/write signals from

the core module when the PCI controlled reset is asserted).

Anyway, I wanted to investigate the avalon resetrequest signal but

I didn't see it show up when adding IUL in SOPC builder -- I guess I should

check how the watchdog does it.

BTW: does the watchdog reset the entire system module (SDRAM

controller et. al.) or just the core itself?

--Scott